AI for verified computing systems
I work on reinforcement learning and large language models for code and hardware that can be proven correct — prompt repair for verified Dafny, multi-agent Verilog generation, and datasets for high-level synthesis verification. Research Assistant at the ESCAD Lab, CSL, ECE, UIUC.
PhD Advisor: Dr. Deming Chen
1308 W Main St
Urbana, IL 61801
Education
Ph.D., Electrical and Computer Engineering
Selected graduate coursework: Statistical Learning Theory, Advanced Topics in Natural Language Processing, LLM Reasoning for Engineering, Computational Complexity.
B.Tech., Electronics and Communication Engineering
Undergraduate research in image restoration and IoT, alongside IEEE student-branch and developer-community leadership.
Research & Professional Experience
Research Assistant — ESCAD Lab, CSL, ECE, UIUC
Reinforcement learning and LLM pipelines for verified code and hardware generation: prompt repair against the Dafny verifier, multi-agent Verilog design, and dataset construction for HLS functional verification.
Applied Scientist Intern — Amazon
Developed an adaptive Specualtive Decoding Algorithm.
Teaching Assistant — ECE 445: Senior Design, UIUC
Guided students through their senior projects. Usually batche sizes > 100
Development Engineering Intern, R&D — Foxconn Interconnect Technology
Worked on real-time Action classification algorithm in live video
Intern Tech II, R&D — Keysight Technologies, India
PDK development team: built and deployed a DRC automation tool.
Student Trainee — Centre for AI & Robotics (CAIR), DRDO
Road segmentation for autonomous robot navigation under the STAR project.
Undergraduate Research Assistant — NIT Patna
Image processing and deep learning with Prof. Ashish Kumar Bhandari — four journal papers and one conference paper.
Front-end Web Development Intern — SatyendraNathBose Technologies
Built company project sites on the MERN stack and WordPress.
Publications
2021 — 2026Toward Engineering AGI: Benchmarking the Engineering Design Capabilities of LLMs
A simulation-grounded benchmark that tests whether LLMs can design, not merely answer engineering questions. EngDesign spans 101 open-ended tasks, nine engineering domains and 473 gradable items, pairing realistic specifications with executable evaluators—from SPICE and MATLAB to structural simulation—to determine whether generated designs satisfy functional constraints and performance goals.
Proof2Silicon: Prompt Repair for Verified Code and Hardware Generation via Reinforcement Learning
An end-to-end synthesis framework that embeds the PREFACE flow: the verifier-driven RL agent optimises prompts until the Dafny is correct, then verified programs are translated to synthesisable HLS. Reaches up to 72% end-to-end hardware synthesis success through Vivado HLS. Presented at SRC TECHCON 2025.
PREFACE: A Reinforcement Learning Framework for Code Verification via LLM Prompt Repair
A model-agnostic framework in which a small language model is trained with RL to repair the prompts given to a frozen LLM, learning from the Dafny verifier's own feedback. Error-guided refinement raises verification success by up to 21% across five LLMs on a 100-task benchmark, with no fine-tuning of the generator.
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
The largest fully open-source hardware-design dataset: 131k Verilog modules drawn from GitHub (102k), VHDL translations (5k) and synthesisable C/C++ (24k), each paired with a natural-language description generated by DeepSeek-R1. Traceable origins and permissive licensing make it usable commercially.
New Solutions on LLM Acceleration, Optimization, and Application
A survey of algorithm- and hardware-level techniques for making large language models cheaper to train, serve, and deploy. Also available as an arXiv preprint.
An Iteratively-refined Dataset for High-Level Synthesis Functional Verification through LLM-Aided Bug Injection
Open-source HLS code with bugs barely exists, so this work curates over 1,500 designs from public benchmark suites, each in a buggy and a bug-free version. The injection method combines in-context learning, retrieval-augmented generation and chain-of-thought, reaching an 84.8% valid single-bug injection rate.
CBLA: Color-Balanced Locally Adjustable Underwater Image Enhancement
Underwater scenes lose colour and contrast to scattering and attenuation. CBLA first restores the distorted colour in RGB space, then works in CIELAB to raise contrast and recover naturalness locally, so information survives rather than being flattened by a global correction.
NSDIE: Noise Suppressing Dark Image Enhancement Using Multiscale Retinex and Low-Rank Minimization
A low-rank model enhances reflectance and illumination at once, so dark scenes brighten without the noise brightening with them: reflectance goes through multiscale Retinex to hold colour, illumination through a camera response model to keep the scene genuine. Shipped as a standalone app and a web portal.
Unevenly illuminated image distortion correction using brightness perception and chromatic luminance
A brightness transfer function derived from the Weber–Fechner law, controlled adaptively by the value and saturation channels in HSV, with image fusion for detail and a colour-contrast function based on the Helmholtz–Kohlrausch effect.
Camera Response Based Nighttime Image Enhancement Using Concurrent Reflectance
Decomposes the image by Retinex theory using a measured adaption model, then enhances illumination with a new camera response model and reflectance locally through a reconstructed histogram equalisation — avoiding both the intensity distortion and the loss of local detail that global methods bring. Designed for hardware or software deployment.
Secure SDN Based IoT Network Through Blockchain for Smart Architectures
Puts a blockchain layer under software-defined networking to authenticate IoT devices in smart-building deployments.
Provoking Medication Adherence With Automated IoT System
A connected dispenser and reminder loop that nudges patients toward taking medication on schedule.
Selected Projects
Verification-Aware RL for Autonomous System Reliability
RL agents and LLMs read telemetry to diagnose reliability faults and propose mitigations, with verification-aware reasoning keeping every proposed fix inside the system's safety constraints.
HWBuilder — Multi-Agent Modular Hardware Design
A labelled dataset of 95k+ verified Verilog designs, and a multi-agent framework of fine-tuned LLMs that generates and optimises microprocessor code against it.
LightKV — Memory-Efficient Long-Sequence Inference
A KV-cache retention algorithm with static masking and information-flow strategies, aimed at the "lost in the middle" failure of autoregressive decoding.
SEE — Transformer-Based Haze Removal
Segments the most heavily hazed regions and dehazes them separately before ensembling, improving on prior single-image methods by up to 45%.
FPGA-Driven YOLO for Rapid Object Detection
An FPGA accelerator for YOLO with cloud integration, tested on ZU702, ZCU102 and PYNQ boards.
Road Segmentation for Robot Navigation
Built at DRDO under the STAR programme: YOLOP and SNE-RoadSeg with grab-cut refinement, evaluated on KITTI, CAIR DRDO and ATR Chitradurga data.